I had an on-going, nagging problem with the dynamic address translation on the 6809 board. The primary bank worked fine, but the secondary just had all sorts of whacky problems. Lots of time staring at the logic analyzer and scope, working through one minor issue after another (not the right speed parts, wrong edge of a signal, etc). Finally it was mostly working except for two 4K pages. This morning I finally connected all the dots, did some experiments and realized the DIP switch to select banks was bad! Shake the board and the combination of good/bad banks kept changing.
A bit of 30 gauge wire to manually connect all the DIP pins and then the memory tests all starting working. In the mean time I’ve gotten quite familiar with the DAT registers and have written some decent tools to check bank select logic and perform memory tests across the banks.
For those not familiar with how SWTPC’s 6809 board did bank selection, they use A12 to A15 as address bits into two high speed TTL RAM chips, the output of which provided the actual A12 to A15, and A16 to A19 for the bank select bits. There are 16 write-only registers from FFF0 to FFFF; FFF0 is for address 0xxxx, FFF1 is for 1xxx, etc.
In each of those registers, the lower 4 bits are the inverse of A12 to A15; the outputs of the RAM chips are inverted. The upper 4 bits are the non-inverted bank select (A16-A19) bits.
So, let’s assume you want to set up 0xxx to be from bank 0 but 1xxx from bank 1. You’d write these values to the DAT registers:
FFF0 = 0F
FFF1 = 1E
The SBUG monitor sets up all 56K for bank 0 by default, but since the Corsham Tech board has 128K, you can map the other bank in and out as desired.
So, the important part is that I’m doing minor cleanup on the board and sending it out for quotes later today. Boards usually arrive within two weeks, which means I’m still on track to having working boards at VCF East. The minor cleanups are making part indicators large enough to read and in places where they can be read; some parts default to having tiny part numbers and also putting the values under the part. That’s fine for a blank board, but I can’t find some parts when debugging a stuffed board!
The 6809 CPU board is alive! This evening I put SBUG into an EPROM and put it into the board, hit reset and started running a memory test…
The assembled board, complete with lifted pins and one visible jumper; the rest of the jumpers are on the back:
The final boards will have about the same layout. Lower right has the 8K EPROM and 128K RAM. Lower left is the baud rate generator and associated configuration jumpers and buffers. Above it is the reset logic, and memory decode. The rest of the board is the 6809 and it’s support logic to make it all work. Oh, and a friendly green power indicator LED in the upper right
The motherboard is an engineering prototype of the 6800/6809 capable mobo that can support either processor type with jumpers.
It’s still not completely done. The other bank of memory still needs to be tested, along with the mapping of the A16-A19 address lines to the SS-50C bus. Once those are done, it’ll be time for final clean-up of the artwork and then ordering production boards.
If you can, please come to VCF East and see both the 6800 and 6809 CPU boards in action!