Month: January 2015

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6809 CPU Boards Ordered!

I finally finished the PCB layout this week, got quotes, and ordered two prototypes of the 6809 CPU boards.  They should arrive in about two weeks, then the fun begins… debugging!  The boards are really dense with 21 ICs and all traces packed onto just two layers.  Any boards more complicated than this will probably go to four layers.  I’m proud to say that this board was routed 100% by hand… about 100 hours to do it!

Trying to get back into more software, I’ve been playing with an admittedly useless program, but it’s been fun: life for the 6800.  I’m very used to thinking in terms of the 6502 addressing modes so it’s been a struggle sometimes writing 6800 code without all the 6502’s cool addressing.  Once Life is done, I’ll put the code on-line.  Nothing amazing, but it has been nice to program just for the fun of it.

Another project that I’ve been thinking about for many years is a KIM-1 motherboard, so over the last few weeks I’ve been jotting down notes and finally starting putting the designs into the CAD package.  This idea kept coming around every time I whacked out a prototype for some board or another, usually disk drives.  Besides the motherboard, I’ve also got a 1 MB RAM card; the motherboard gives four extra address bits.  An EPROM card for disk I/O and maybe a BASIC interpreter is next.

I am not a sports fan, so while many people will be watching the “big game” tomorrow I’ll either be in front of the CAD package or debugging the Life program.

 

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Lots of Stuff in Progress

The new and improved SS-50 motherboard engineering samples arrived and have tested out nicely with the 6800 CPU.  I’ve been using one of them non-stop for use in the lab and they work great.  A few features:

  • Base address for the I/O slots can be set to either 8000 (6800) or E000 (6809)
  • The number of bytes allocated for each I/O slot can be set to 4 (6800) or 16 (6809)
  • Three SS-50 slots

It’s no secret I’ve been slowly working on a 6809 based SS-50 system so the motherboard is the first step.  Until a working 6809 CPU board is ready there’s no way I can test it completely, so there are only engineering prototypes now.

Along with the new motherboards are SS-30 bus extenders that add slots 2-7.  This works with the existing motherboards too.

The SS-30 SD cards have arrived and don’t work, but I’ve yet to spend the time to debug them.  Again, these are engineering samples, so this is where bugs are shaken out and then production boards are ordered.

The 6809 CPU board is designed and I’ve been breadboarding portions of it.  There are still too many chips so I’m trying to simplify the logic a bit while still using 7400 series chips.  Using a small CPLD would greatly simply the design and get rid of all the glue logic but then it’s less vintage and many people won’t be able to make changes.

The design is nothing amazing, but makes a nice system:

  • 6809 running at 2 MHz
  • An 8K EPROM (they’re easy to come by) but only the top 2K (normal) or 4K will be enabled.  The default is 2K but the user can install one jumper to turn on the EPROM from F000 to FFFF.
  • Baud rate generator, but the shared Sx/baud rate pins are each selected by a jumper so you can add from zero to four of the extended addressing pins.
  • SWTPC compatible Dynamic Address Translation.  Extends the address bus by four bits.
  • Baud rate pins moved a bit so 1200, 2400, 4800 and 9600 can be put onto a single pin, freeing up the rest for extended address bits.
  • 128K of RAM!  Definitely not vintage.  It is selectable in 8K chunks for banks 0 and 1.
  • Uses standard SBUG.  I might add extensions like we did with SWTBUG but it remains to be seen.

I’m really hoping to get the chip count down, finalize a PC board and order prototypes within a week.  The goal is to have production versions at VCF East in mid-April.