Month: February 2015

The 6809 CPU board is alive!  This evening I put SBUG into an EPROM and put it into the board, hit reset and started running a memory test…

The assembled board, complete with lifted pins and one visible jumper; the rest of the jumpers are on the back:

The final boards will have about the same layout.  Lower right has the 8K EPROM and 128K RAM.  Lower left is the baud rate generator and associated configuration jumpers and buffers.  Above it is the reset logic, and memory decode.  The rest of the board is the 6809 and it’s support logic to make it all work.  Oh, and a friendly green power indicator LED in the upper right 😉

The motherboard is an engineering prototype of the 6800/6809 capable mobo that can support either processor type with jumpers.

It’s still not completely done.  The other bank of memory still needs to be tested, along with the mapping of the A16-A19 address lines to the SS-50C bus.  Once those are done, it’ll be time for final clean-up of the artwork and then ordering production boards.

If you can, please come to VCF East and see both the 6800 and 6809 CPU boards in action!

 

A clip of a test message spewing out the serial port:

That’s TeraTerm on one of the PCs in the lab.  The test program sets up the address translation registers and then sits in a loop outputting the message over and over again.  Not very exciting, but it does test more of the board.  The entire ROM area is working, as is the I/O buffering and bus signals needed to access the I/O devices.

There are still things to test, such as the on-board 128K of RAM and the four extended address bits.  This weekend was busy with a lot of Boy Scout activities and this coming week is loaded with lots of meetings, but I should have some decent progress.

All of the cuts/jumpers so far have been rolled into the schematic and board layout, so if everything else tests positive, I should be able to order real boards soon.

My goal is still to have production boards ready by VCF East in April.

 

Getting the dynamic address translation (DAT) going was a major headache.  Everything that could have gone wrong did go wrong, but tonight it was finally working!

Three major pieces need to be tested/debugged still:

• Full EPROM (right now all code is in the top 256 bytes)
• Communication to/from the I/O bus
• On-board RAM

I’m still pushing to have this debugged and production ready for VCF East in mid April.  My full time consultant contract keeps me pretty busy so another consulting contract and the vintage computer projects are done on evenings and weekends.

I’ll add photos of the fully stuffed board in a few days.