I contracted out for a new web page design and will probably switch over to it during the next few weeks. It’s more professional looking, focused more on my consulting business… that’s where I make my real money, while the vintage products are more for fun.
Once the switch happens, we’ll be tweaking things for a while.
The 6809 production boards are in and I’ve been running one in the lab for about week now with no problems. I’ve also switched to the new motherboard that supports both the existing 6800 and the new 6809 CPU cards.
It’s a quiet Sunday morning so I’m taking a break from building boards to focus on documentation for the new boards.
VCF East is just a few weeks away so I’m hustling to build and test boards for the show. Since there has been so much emphasis on the new boards, I won’t have any cool software to show, but maybe I can pull some stuff off the net to have running at the show. Before the 6809 was done I spent some time writing a version of Conway’s Life for the 6800 and that was fun to just watch.
Prices have not been set yet. Boards won’t be for sale until VCF East, then they can be purchased on-line.
I had an on-going, nagging problem with the dynamic address translation on the 6809 board. The primary bank worked fine, but the secondary just had all sorts of whacky problems. Lots of time staring at the logic analyzer and scope, working through one minor issue after another (not the right speed parts, wrong edge of a signal, etc). Finally it was mostly working except for two 4K pages. This morning I finally connected all the dots, did some experiments and realized the DIP switch to select banks was bad! Shake the board and the combination of good/bad banks kept changing.
A bit of 30 gauge wire to manually connect all the DIP pins and then the memory tests all starting working. In the mean time I’ve gotten quite familiar with the DAT registers and have written some decent tools to check bank select logic and perform memory tests across the banks.
For those not familiar with how SWTPC’s 6809 board did bank selection, they use A12 to A15 as address bits into two high speed TTL RAM chips, the output of which provided the actual A12 to A15, and A16 to A19 for the bank select bits. There are 16 write-only registers from FFF0 to FFFF; FFF0 is for address 0xxxx, FFF1 is for 1xxx, etc.
In each of those registers, the lower 4 bits are the inverse of A12 to A15; the outputs of the RAM chips are inverted. The upper 4 bits are the non-inverted bank select (A16-A19) bits.
So, let’s assume you want to set up 0xxx to be from bank 0 but 1xxx from bank 1. You’d write these values to the DAT registers:
FFF0 = 0F
FFF1 = 1E
The SBUG monitor sets up all 56K for bank 0 by default, but since the Corsham Tech board has 128K, you can map the other bank in and out as desired.
So, the important part is that I’m doing minor cleanup on the board and sending it out for quotes later today. Boards usually arrive within two weeks, which means I’m still on track to having working boards at VCF East. The minor cleanups are making part indicators large enough to read and in places where they can be read; some parts default to having tiny part numbers and also putting the values under the part. That’s fine for a blank board, but I can’t find some parts when debugging a stuffed board!
